ASIC 과 FPGA용 혼합 언어 시뮬레이션 분야의 선두 주자인 미국 Aldec사는 1984년 Dr. Stanley M. Hyduke에 의해 설립된 이후에 low density FPGA를 타겟으로 하는 entry level users들을 비롯하여 Assertion-based verification design 및 hardware-based acceleration처럼 high performance를 요구하는 user 까지 수용할 수 있는 다양한 HDL 검증 툴을 제공하고 있습니다.
이러한 검증 툴들은 세계적으로 3,000개 이상의 회사에서 사용되고 있으며 현재 한국에서는 대학교 및 중소기업들에서 많이 사용되고 있으며 오랜 경험 및 기술을 바탕으로 대기업에서도 그 Needs가 점차 증가되고 있습니다.
Aldec 사에서 제공되는 제품으로써는 윈도우 운영시스템상에서 FPGA/CPLD 및 ASIC design을 검증해주는 Active-HDL Simulator가 있고 윈도우 , 리눅스 및 유닉스 운영시스템상에서 FPGA/CPLDs 및 ASIC개발을 하고 있는 고객들로부터 사용되고 있는 Mixed VHDL, Verilog, SystemC, SystemVerilog and Assertion-based simulator인 Reviera가 있습니다 . 또한 Hardware Embeded Simulation 툴인 HES이 있습니다.
Today’s FPGA design teams require innovative solutions that foster team productivity and enable rapid deployment at every stage of design development - from Design Entry to Place and Route. Aldec offers the industry’s most comprehensive, all-in-one platform for FPGA design development to meet the increasing demands of the FPGA development process:
Hardware Emulation Solutions
HES-DVM™ is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES-DVM allows for multiple modes of verification and validation including:
Codasip Studio is a highly automated, fully integrated, development environment covering all aspects of Application Specific Instruction-set Processor (ASIP) design. Starting with a high-level description of the processor written in CodAL(Codasip’s processor description language), users are able to generate the design implementation, verification environment, virtual system prototype, and complete programming tool chain.
In addition to its ASIP design capabilities, Codasip Studio includes powerful multiprocessor programming, debug and profiling - enabling the most complex ASIP-based designs to be managed with ease.
CodAL Processor Description Language
CodAL is a highly structured, hierarchal, C-like architectural description language for processor design. The language can describe a wide range of processor styles including RISC, CISC,
VLIW, and DSP.
In addition to supporting processor descriptions, CodAL is able to describe complex multi-processor environments including interconnect and peripherals.
Codasip believes in open standards and open formats and thanks to a unique software architecture we are able to automatically generate state of the art redistributable development tools based on LLVM, GDB, QEMU and much more.
The tool chain is generated from the ASIP’s CodAL model and includes full support for specialized ASIP extensions, complex SIMDs, and advanced latency aware compilation for VLIW architectures. Generation of the tool chain requires only the Instruction Accurate (IA) portion of the model, which is something that typically takes only a few days to create for an existing processor.
In addition to the tool chain a comprehensive profiling environment is generated to enable application profiling on the target architecture to determines parts best suited to acceleration with new instructions. As instructions are added profiling tools can be used to see how effective the changes have been.
High performance RTL
Codasip Studio delivers a natural iterative approach to design, making it simple and easy to move from an algorithm to the complete ASIP implementation.
Advanced high level synthesis technology allows Codasip Studio to generate processors that exceed the performance of hand-optimized designs. The ability to add application specific instructions that are fully integrated into the processor architecture delivers performance well above traditional extensible processor approaches.
Codasip Studio generates a complete UVM verification environment for both automated processor validation, as well as integration with the SoC verification environment.
Additionally, Codasip Studio generates QEMU and OVP models of the processor, allowing development teams to run software on the ASIP platform well ahead of silicon availability.
As SoC’s become increasingly complex, even sub-systems often contain multiple processors working together to implement a single capability. To support the creation of these complex application specific subsystems, Codasip Studio includes a comprehensive set of tools for multiprocessor programming and debug.
With the growing complexity and size of today’s FPGA and ASIC designs, requirements have also grown exponentially, and methodologies to effectively manage and track requirements have never been more crucial to produce high-quality, reliable and safe products on time and within budget. Safety-critical designs seeking DO-254 compliance face greater challenges with a strict requirements-based design and verification process that must be followed to ensure that the product built functions as intended based on the requirements.
Aldec’s requirements lifecycle management tool suite streamlines the requirements engineering process from capture to traceability, analysis to reporting and design to test results management. FPGA/ASIC requirements are automatically traced down to HDL design and testbench sources ensuring that each requirement has been fully implemented, covered and verified. Requirements coverage gaps and as well as unused HDL functions are easily exposed and reported using multi-directional traceability.
Recently, FPGA vendors have released SoC FPGAs integrating ARM®-based microprocessors with their respective powerful FPGA technology in a single die for a more robust integration of embedded designs. Designers building a complex embedded design need only a single IC on board that contains microprocessor, DSP and FPGA optimizing system performance, flexibility and scalability. SoC FPGAs such as Xilinx® Zynq™ contains ARM Cortex™-A9 and Xilinx 7000 series FPGA technology with varying capacity of logic cells, BRAM, DSP slices and I/O pins.
Aldec’s specialized tools for design and verification of FPGAs boost productivity and help applicants achieve DO-254 compliance: Spec-TRACER, ALINT-PRO, Active-HDL and DO-254/CTS. Aldec’s tools have been implemented and deployed by several major avionics companies, accepted by certification authorities, and proven to decrease FPGA design and verification cycle from months to weeks.
ALINT-PRO™ - Design Rule Checking
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
HES™- FPGA Boards
HES™ is a SoC/ASIC pre-silicon prototyping solution for hardware verification and software validation teams and the High Performance Computing (HPC) platform for algorithms acceleration. The boards are based on largest Virtex-7 and Virtex UltraScale FPGA and appear in single or multi-FPGA configurations and can be interconnected on a backplane board providing up to 663 Million ASIC gates.